Data processing devices typically employ a load/store module to transfer data between a processor, a local cache, and a common device memory. The load/store module generally interfaces with a bus in order to read or write data to the common memory. In addition, the load/store module typically maintains coherency information for the local cache. In particular, for load or store instructions received from the processor, the load/store module selects from a range of possible bus transactions according to whether data is to be read or written, and based on the intended impact of the transaction on memory coherency. Multi-processor systems typically employ a different load/store module for each processor, with the bus transactions from each load/store module impacting the coherency of each local cache. Further, in multi-processor systems the time at which each bus transaction is serviced can be subject to a large degree of uncertainty, so that simulation of bus behavior is difficult.
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